Recent advances in the state-of-the-art in microcircuits involve two interrelated parameters germane to the Flexible Electrical Test Fixture (FETF) for integrated circuits on prototype and production printed circuit boards. These advances consist of increases in microcircuit density, and increases in microcircuit switching speed.
Increasing the microcircuit density in the mechanical implementation of a design involves the placement of more functionality into a single integrated circuit, and bringing the integrated circuit packages on-board closer together. The Surface Mount Device (SMD), allowing high pin counts with close proximity mounting, was created for this purpose. Increased switching speed increases transmission line effects in the circuit. Switching speed increases are gained by reducing inductance and capacitance in the transmission lines which is primarily accomplished through the use of the higher density packaging described above.
The process of developing an electronic design from concept through finished product usually requires a prototyping stage. This prototyping stage can involve a physical implementation of all or part of the electronic design on a printed circuit board. This stage of development is used to demonstrate the validity of the design and also exposes design flaws (bugs) that need to be addressed prior to the manufacture of production quantities of the printed circuit board.
Ideally, the prototype printed circuit board is made as similar as possible to the anticipated production version in an attempt to preclude new "bugs" from appearing in the production board which were not present in the prototype printed circuit board. However, because of the testability requirements of these boards, the prototype printed circuit board requires allowances for the circuit designer to gain access to pins on the integrated circuits used in the design. Usually, the designer will connect either logic analyzer or oscilloscope probes to the pins of his circuit during the testing process. This connection between integrated circuit pins and logic analyzer or oscilloscope probes can be accomplished in a number of ways currently existing in the art:
1) test points associated with each integrated circuit pin to be monitored are designed onto the printed circuit board, PA1 2) connection is made via a single tip probe adapter, PA1 3) connection is made via a clip-on probe adapter, PA1 4) connection is made via a socketable probe adapter. PA1 1) a flexible printed circuit board, PA1 2) a first attachment mechanism having attachment points, generally, but not necessarily having the same number of attachment points arranged in the same pin pattern of the integrated circuit, for attaching the pins of an integrated to the flexible printed circuit board, and PA1 3) one or more test point mechanisms mounted on the flexible printed circuit board in one or more areas adjoining the first attachment mechanism, each test point mechanism having a number of test points. The total number of test points is, generally, but not necessarily, equal to the number of pins of the integrated circuit. Each test point is electrically connected to one or more of the attachment points.
The first method can provide access to as many or all of the pins of the integrated circuits of a design at the discretion of the designer. Any integrated circuit pin which is not included as a test point may be difficult to test during the prototyping phase. Further, the inclusion of test points, especially a large number of test points, creates an assembly which is usually different from the production version in that the number of test points required for the prototype is much larger than the limited requirement on a production board. Further, inclusion of these test points can add substantial capacitance and inductance to the transmission structure between integrated circuits, and can cause an otherwise competent design to malfunction. Assemblies with a large number of test points are physically larger than a counterpart with no or a limited number of test points.
The second method requires a fine tip or small clip-on adapter suitable for individual pins. The method is restrictive and cumbersome in that it allows test of only a limited number of pins at the same time. Some integrated circuits are not testable in this way due to the pitch of the pins, or the placement of pins under the body of the integrated circuit.
The third method clips an adapter onto the pins of the integrated circuit. As in method two, some integrated circuits are not testable in this way due to the pitch of the pins or the placement of pins under the body of the integrated circuit. For high pitch pins, this method is characteristically susceptible to shorting pins together, and is therefore unreliable. Further, substantial side clearance is required in the board layout.
In the fourth method, one or more of the printed circuit board's integrated circuits are plugged into a socket for normal operation. For test, the integrated circuit is removed from its socket and plugged into a socketable probe adapter. The socketable probe adapter is then plugged into the original integrated circuit's socket. Sockets are classically unreliable in the long term, and add extra lead length, capacitance and inductance to the circuit. Some integrated circuits cannot be socketted. The sockets also require substantial side clearance in the board layout. When under test, the integrated circuit is socketted into the adapter which is in turn socketted into the board's socket. Two sockets are involved in connecting the integrated circuit to the printed circuit board. Inductance and capacitance are further increased. Some high speed designs which would otherwise be competent will fail to perform or show bugs which would not exist in a layout without sockets.
The third and fourth method are currently widely used for testing integrated circuits. Because there are many integrated circuit foot-prints, many different adapters are needed for test. They are individually expensive, but are reusable from design to design. However, because of repetitive mechanical insertion and extraction, these "reusable" adapters become unreliable with age.
Objects
The current state-of-the-art in integrated circuit testing has no method for connecting an oscilloscope of logic analyzer to a circuit under test in an unintrusive way. The currently existent methods cannot be universally employed and either effect the operation of the circuit, the physical layout of the design, or are unreliable.
Accordingly, it is a first object of the present invention to provide a n electrically unintrusive method to connect a logic analyzer or oscilloscope to any pin of any integrated circuit, such that there is negligible difference between the operation of the integrated circuit under test (prototype) conditions and under normal operation (production) conditions due to this connection.
It is a second object of the present invention to allow the connection of all of the pins of any integrated circuit to a logic analyzer or oscilloscope.
It is a third object of the present invention to allow the physical construction of a prototype printed circuit board to be identical to the production version of the printed circuit board.
It is a fourth object of the present invention to allow the process of prototype printed circuit board development to be identical to that of the production version, less the FETF, of the same printed circuit board in the placement of integrated circuits and the fabrication of the printed circuit board itself.
It is a fifth object of the present invention to provide a reliable electrical test fixture for integrated circuits which, by its nature and cost, is disposable after its term of use on a single printed circuit board.
A completely new and innovative method for the attachment of a logic analyzer or oscilloscope probes to integrated circuits under test is defined.
Advantages
The present invention provides a generic method for the attachment of logic analyzer or oscilloscope probes to any integrated circuit. In this attachment, the FETF does not insert any meaningful circuitry between the integrated circuit and the printed circuit board. Therefore, the FETF does not add significant capacitance, inductance or lead length between in circuit devices or to the process of in-circuit integrated circuit testing. High speed circuits are not made inoperative through the addition of the FETF. Because of its flexible construction, the FETF does not substantially increase the side clearance requirements in the board layout and thereby allows higher packaging densities in both prototype and production versions of a design. Because of the unintrusive nature of the FETF, prototype board layouts can be identical to that defined for the production version. Because the prototype and production versions of a printed circuit board are identical, manufacturing processes can be the same for the two assemblies, with the FETF removed for the production version. Further, the FETF can be made very inexpensively relative to adapter technology, and because it is soldered in place, the FETF provides a reliable connection for the life of its use on prototype and production printed circuit boards. Because it is inexpensive and that it is soldered in place, the FETF can be included as an integral part of the production printed circuit board.
Novel Difference Between the Present Invention and the Art
The present invention provides for the mechanical and electrical insertion of a flexible printed circuit board between the pins of an integrated circuit and the rigid printed circuit board to which it would otherwise b e mounted. Test points are attached to the flexible printed circuit board in areas adjoining the integrated circuit's attachment points, and are electrically connected to these attachment points. The areas which contain test points are folded above the integrated circuit making the test points accessible to the probes of an electronic test instrument.
No other existing method (i.e. test points, single tip probe adapter, clip-on probe adapter, or socketable probe adapter) provides for signal access and pick-off from between the integrated circuit and its external printed circuit board. Neither do any of the existing methods use the flexible printed circuit board to bring the signals of the integrated circuit to a position above the body of the integrated circuit where they are easily accessible to the probes of an electronic test instrument and decrease the side clearance required to use a test fixture.
Further, as all of the attachment points can be of a solderable type, the electrical connection between the integrated circuit and the external printed circuit board is substantially lower in resistance, inductance and capacitance and more reliable than the clip-on and socketable alternatives. When used with solderable attachment points, the invention is essentially a single use, disposable test fixture while the clip-on and socketable alternatives are reusable and become unreliable with age.